Specifications Schematic Symbol Simulation Layout DRC Extraction LVS Post-layout Simulation
Introduction to VLSI Design

This site contains a complete on-line tutorial for a typical bottom-up design flow using CADENCE Custom IC Design Tools (version 97A). The examples were generated using the HP 0.6 um CMOS14TB process technology files, prepared at North Carolina State University (NCSU) and made available through MOSIS.

Please click on any box in the design flow (below) to see a detailed description of the corresponding design step, and to view the design examples.

Please note that all images in the example pages can be enlarged by clicking on them.

Tutorial Flow



a production of


VLSI CAD Laboratory


Analog/Digital Microelectronics Group

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Ilhan Hatirnaz 11/01/1998